The present invention relates to sense amplifiers for use with nonvolatile semiconductor memories. More specifically, it relates to the structure of a reference memory cell used in establishing a reference voltage for a sense amplifier.
Within a memory IC, sense amplifiers are used to read data from a target memory cell within a memory array. These amplifiers are typically categorized as single-ended sense amplifiers or differential sense amplifier. Single-ended sense amplifiers are commonly used in memories having a single-bit per memory cell. Examples of single-bit per cell memories are EEPROM and Flash EPROMs. These single-bit per cell memories store only one of the true value or compliment value of a datum item in each memory cell. This is in contrast to dual-bit per cell memories such as SRAMs, which store both the true and complement value of a datum item in each memory cell. Having both the true and complement value of a datum item within each memory cell facilitates and speeds up the reading of a memory cell since one can identify the stored datum item by simultaneously accessing both true and complement bits and simply determining which has the higher voltage potential. Stated more clearly, SRAMs use differential amplifiers to read each memory cell, and identify the logic state stored within a memory cell as soon as the direction of the voltage imbalance, representative of the true and complimentary data stored within the memory cell, is determined. Since single-bit per cell memories do not have the luxury of knowing the compliment of the stored datum item, their single-ended sensing circuitry requires a different, and more critically balanced approach.
Use of a differential sense amplifier in a nonvolatile memory would provide a big boost in reading speed, but would require two memory storage devices per memory cell, one for the true data and another for the complement data. This would reduce the memory capacity at least by 50%. It is more likely that the reduction would be much greater because of the need to accommodate additional bitlines, equalization circuitry, more complex program and erase circuitry, and other circuitry required to implement a dual-bit per memory cell architecture. Therefore, nonvolatile memories generally use single-ended sense amplifiers.
With reference to FIG. 1, a single-ended sensing circuit 12 suitable for use with a single-bit memory cell is shown 14. Target single-bit memory cell 14 is depicted as a single floating gate transistor 16. Sensing circuit 12 determines the logic state stored within target memory cell 14 by sensing a potential difference between a sense line 18 coupled to target memory cell 14 and a reference line 20 coupled to a reference memory cell 22. The potential of sense line 18 is dependent on the logic state, high or low, of the datum stored within target memory cell 14. Typically, if the potential of sense line 18 is higher than that of reference line 20, then target memory cell 14 is read as having a logic low state, and if the potential of sense line 18 is lower than reference line 20, then target memory cell 14 is read as having a logic high state. Therefore, it is important that the voltage potential of reference line 20 be maintained at a value intermediate the logic high and logic low voltage potentials of target cell 14.
At first glance, it would appear that the reference voltage on line 20 could be produced with a constant voltage generator, but this is not preferred. The potential at sense line 18 is affected not only by the potential at the gate of floating gate transistor 16, but also by the architecture of the memory. The capacitive loads of target memory cell 14 depend on its physical structure and on its location within a larger memory array. These capacitive loads, in turn, affect the current sourcing capability of target memory cell 14 and thereby the potential at sense line 18.
Therefore, an effort is made to help reference line 20 reflect these capacitive loads in order to better track the logic high and logic low voltages of target memory cell 16. A typical method of tracking these effects on the logic high and logic low voltages of a target memory cell is to use another memory cell, i.e. a reference memory cell 22, to produce the voltage potential for reference line 20. The idea is that since the reference memory cell 22 hag a similar structure as target memory cell 14, its behavior will be similar to that of target cell 14. The potential of reference line 20 is therefore dependent on the current sourcing value of reference cell 22.
Various methods of using a reference cell for producing the reference voltage for use with a single-ended sensing circuit are known in the art. Some of these methods are discussed in U.S. Pat. No. 5,572,474 to Sheen et al., U.S. Pat. No. 5,608,679 to Medlock et al., and U.S. Pat. No. 5,642,308 to Yoshida.
Applicants have found, however, that existing methods of generating a reference voltage on reference line 20 are not stable over the life of the memory IC. This is in part due to reference cell 22 using a floating gate transistor 26 to produce the reference voltage. Although using a floating gate transistor 26 within reference cell 22 is advantageous because it provides a better balance with the floating gate transistor 16 of target memory cell 14, floating gate transistor 26 introduces additional problems that may complicate generating an accurate reference voltage on reference line 20.
Since the threshold voltage of reference cell 22 should not changed, reference cell 22 is isolated from program and erase circuitry used in altering the state of the storage memory cells 14 in a main memory array. Reference memory cells, in general, are constructed with no charge on their floating gate 28, and the charge level on their floating gate 28 is not intended to change since they are not connected to any programming or erasing circuitry. If desired, the threshold voltage level of reference cells may be adjusted by adjusting the substrate doping concentration of their channel region.
Unfortunately, there are several factors that can alter the charge level of a reference cell""s floating gate 28. Floating gate transistors, in general, are susceptible to read disturb problems that can change the amount of charge on a reference cell""s floating gate 28, which results in a change in its threshold voltage. This can result in a change in the cell""s reference current value, which in turn changes the voltage value of reference line 20. Due to the critical balancing of the sensing circuit 12, a voltage change in sense line 20 can, at best, slow down sensing circuit 12, and at worst, cause it to read erroneous data.
Additionally, Applicants have identified another source of error associated with the use of a floating gate reference cell 22. The manufacturing of nonvolatile memory ICs often requires the use of plasmas. Plasma has an intrinsic electric charge associate with it that will typically alter the charge on the floating gate of a nonvolatile memory cell during the manufacturing process. To accommodate for this change in the floating gate charge, the main memory array is typically subjected to an erase sequence at the end of the manufacturing process. However, since reference cell 22 is isolated from the main memory""s program and erase circuitry, it is not erased in this erase sequence and its floating gate is not brought to a neutral position. One method of addressing this problem is to subject the entire memory IC to ultra violet, UV, light for a predetermined period of time at the end of the manufacturing process. Exposure to UV light can erase reference cell 22, but one cannot be certain that reference cell 22 is fully erased. As a result, sense amplifier 12 must accommodate for such variations, which necessarily slows it down.
As the density of nonvolatile memories continues to increase and their speeds requirements continue to rise, every factor affecting the speed performance becomes more critical. It is an object of the present invention to provide a faster, and more process insensitive, sense amplifier.
It is another object of the present invention to generate a reference voltage for use with a sense amplifier that is not affected by threshold voltage changes in the sense amplifier""s reference cell, but which still accurately tracks variations in a target memory cell within the main memory array.
It is still another object to provide a reference cell that compensate for layout variations in a compact EEPROM memory structure.
The above objects are met in a single-ended sense amplifier having a reference cell circuit whose structure mirrors that of the main memory array, but which does not rely on accurate measures of charge stored within a floating gate to establish a reference voltage. The sense amplifier""s reference voltage is dependent on the level of current sourced by its reference cell. This level of current is in turn dependent on the reference cell""s threshold voltage, structural characteristics and physical layout. Since the structure of the reference cell is similar to that of the target memory array, the reference voltage tracks changes over the life of the target memory array. To better track the physical layout of a target memory cell within the main memory array, the present reference cell circuit include two different reference cell layouts. A first reference cell layout corresponds to the layout of a target memory cell in an even numbered row, and a second reference cell layout correspond to the layout of a target memory cell in an odd numbered row. This permits even closer tracking of cell layout variations of target cell within the main memory array.
A reference cell""s threshold voltage, and thereby its current sourcing capability, is also dependent on the amount of charge on its floating gate. As explained above, the charge on the floating gate establishes a threshold voltage for a memory cell, which determines how much current it sources in response to a voltage applied at its control gate. Applicants have found, however, that reliance on the floating gate to establish the threshold voltage of the reference cell can introduce unexpected errors.
During the manufacture of a memory IC, it is often required that the memory IC be submitted to a plasma process step. This, for example, may be part of a plasma etchant step. Plasma has an associated charge, and the floating gates of all floating gate transistors will be partly charged during a plasma step. This does not severely affect the main array since it generally undergoes an erase sequence during initial testing of the memory IC, which removes any accumulated charge from their respective floating gates. The reference cells, however, do not under this erase step. Indeed, memory IC""s typically do not have erase circuitry coupled to the reference cells. To reduce the charge trapped within the floating gates after manufacture, the memory IC is typically subjected to an ultra violet erase step. Ideally, the UV light should remove the charge within each memory cell and bring all floating gate within an IC to a known charge state. This is critical for the reference cell since it must generate a known, and precisely controlled current. Any variation from the expected value will slow down the sensing of a cell since the tolerance margins would have to be relaxed. It has been found, however, that not all referenced cells are fully erased during this UV light erase step, which prevents the IC from having its read margins tightened and thereby its read access time shorten.
Even if the charge in a the reference cell can be initiated to known low values, the charge on the floating gate is prone to vary over the life of the memory. In other words, the charge on the reference cell will change over time as a result of normal read operations. This is due to various phenomena, such as an error known as read disturb, which can cause a small change in the amount of charge stored within a floating gate by virtue of repeated read operations. Since the reference cell is read every time any memory cell within the main memory array is read, the reference cell is more susceptible to read disturb problems.
The present invention addresses both of the above listed, floating gate related, sources of error by not allowing the reference cell""s floating gate to float. The reference cell""s control gate is connected to the cell""s floating gate. This permits the present invention to eliminates any errors resulting from charge variations on a floating gate. Furthermore, this also allows a better control of the exact voltage coupling of the floating gate to the control gate. Floating gate cells typically having an 85% to 90% coupling ratio between their control gate and their floating gate, and this coupling ratio cannot be controlled to an exact value. Additionally, the effective coupling margin is likely to change over the life the cell as the charge on the floating gate varies. By offering a precise coupling ratio of 100%, the present invention can further tighten the operating margins of the memory IC and thereby increase its speed.
Since the amount of charge on the floating gate is controlled by a direct line from its control gate, it is not susceptible to charge buildup or charge leakage on the floating gate. Thus, the present reference cell is unaffected by charge buildup caused by plasma steps in the manufacturing process. This also makes the reference memory cell resistant to other floating gate related errors such as read disturb and aging. The amount of charge on the floating gate is directly adjusted by a digitally controlled, constant reference voltage source coupled to the control gate of the reference cell""s control gate. This permits the present invention to tighten the operating margins even more, resulting in greater speed gains.
Use of a reference cell having its control gate tied to its floating gate allows the present invention to focus on tracking the architectural layout of the target memory cells within the main memory array. The reference cell of the present invention tracks a target memory cell""s structure, ion implantation profile, layout, etc. to assure an accurate comparison for read operations, without being prone to the errors associated with the use of a floating gate structure.
Preferably, the reference cell circuitry of the present sense amplifier consists of two reference cells to mimic two floating gate transistors on adjacent rows of a target memory array sharing the same bitline and the same source line. It has been found that the memory array layout can affect the reading of a targeted memory cell. A first target memory cell lying within a first row may produce a different voltage on its bitline, than a second target memory cell having the same stored data value and coupled to the same bit line but lying on an adjacent row. This is in part due to the physical layout orientation of the two cell which causes them xe2x80x9cto seexe2x80x9d different capacitive load levels. To compensate for this, the layout of the two reference floating gate transistors of the present invention is constructed in a manner corresponding to the memory layout of a target memory cell on an even number row coupled to an adjacent target memory cell in an odd number row. The digitally controlled constant reference voltage source of the present invention can determine whether an even number row or an odd number row is being addressed, and activate only the reference floating gate transistor having a layout corresponding to the appropriately targeted even or odd numbered row. This permits the present invention to better match voltage variations within the main memory array and thereby further tighten operating margins to achieve higher speeds.